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Edition Infineon Technologies AG May All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

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By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG.

If they fail, it is reasonable to assume that the health of the user may be endangered. The IC offers a high level of integration and needs only a few external components. Additionally there is a power down feature to save battery life.

Package Outlines. Pin Definition and Function. Functional Block Diagram. Functional Blocks. Data Filter Design. Quartz Load Capacitance Calculation. Quartz Frequency Calculation. Data Slicer Threshold Generation. Test Board Layouts. Bill of Materials. FSK mode, 5. ESD-protection circuits are omitted to ease reading. The noise figure of the LNA is approximately 3dB, the current consumption is ?

The gain can be reduced by approximately 18dB. This voltage is compared internally with the received signal RSSI level generated by the limiter circuitry. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin Pin 24 which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.

The optimum choice of AGC time constant and the threshold voltage is described in Section 4. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground via a capacitor. The IF output is internally consisting of an emitter follower that has a source impedance of approximately ?

The VCO is including on-chip spiral inductors and varactor diodes. Depending on whether high- or low-side injection of the local oscillator is used the receive frequency ranges are to and to MHz or to and to MHz see also Section 4. No additional external components are necessary. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. In case of operation in the to MHz range, the signal is divided by two before it is fed to the mixer.

The overall division ratio of the divider chain can be selected to be either or 64, depending on the frequency of the reference oscillator quartz see below and Section 4. The loop filter is also realised fully on-chip. It has a typical input impedance of ? This signal is used to demodulate ASK-modulated receive signals in the subsequent baseband circuitry. The Limiter output differential signal is fed to the linear phase detector as is the output of the The demodulator gain is typically ?

The passive loop filter output that is comprised fully on chip is fed to both the VCO and the modulation format switch described in more detail below. This signal is representing the demodulated signal with high frequencies applied to the demodulator demodulated to logic ones and low frequencies demodulated to logic zeroes.

Please note that due to this behaviour a sign inversion of the data occurs in case of high-side injection of the local oscillator at receive frequencies below or MHz, respectively.

See also. The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL pin Pin 15 as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits.

The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 4. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4. This allows for a maximum receive data rate of up to kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible.

The output delivers a digital data signal CMOS-like levels for sbsequent circuits. The self-adjusting threshold on pin 20 its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4. An external RC network is necessary. This output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode.

The maximum output current is typically ? A, the discharge current is lower than 2? A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin Pin 27 as shown in the following table.

The supply current drawn in this case is typically 50nA. R1 R2 Uth re s h old Pins: 24 23 20k? RSSI 0. As shown in the following figure the threshold voltage can have any value between approximately 0. Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.

It should be noted that the output of the 3VOUT pin is capable of driving up to 50? As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values.

The sum of R1 and R2 has to be k? R1 can thus be chosen as k? A1 and a threshold voltage of 1. In order to achieve high gain mode operation, a voltage higher than 2. In order to achieve low gain mode operation a voltage lower than 0. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.

Examples: 6. This signal is divided by 2 before applied to the mixer in case of operation at MHz. This local oscillator signal can be used to downconvert the RF signals both with high- or lowside injection at the mixer. The resulting receive frequency ranges then extend between and MHz or between and MHz.

Low-side injection of the local oscillator has to be used for receive frequencies between and MHz as well as high-side injection for receive frequencies below MHz.

Corresponding to that in the MHz region low-side injection is applicable for receive frequencies above MHz, high-side injection below this frequency. Therefore for operation both in the and the MHz ISM bands low-side injection of the local oscillator has to be used. Then the local oscillator frequency is calculated by subtracting the IF frequency Please note that no sign-inversion occurs in case of reception and demodulation of FSK-modulated signals.

The overall division ratios in the PLL are 64 or in case of operation at MHz or 32 and 64 in case of operation at MHz, depending on the crystal frequency used as shown below. The quartz frequency in case of low-side injection may be calculated by using the following formula:? RF - QU r receive frequency local oscillator PLL frequency?


TDA5210 Receiver. Datasheet pdf. Equivalent



TDA5210 Datasheet PDF



TDA5210 Datasheet PDF




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