ART VERIFICATION SYSTEMVERILOG ASSERTIONS PDF

The book demonstrates how SVA can be harnessed to implement effective, assertion-based verification. It teaches the SVA language by explaining its usage in the context of practical verification issues. SVA syntax and features are explained in simple and easy-to-understand language. The usage of each construct is illustrated with both simple examples and examples drawn from common verification problems.

Author:Vudojin Faeramar
Country:Andorra
Language:English (Spanish)
Genre:Software
Published (Last):11 January 2004
Pages:496
PDF File Size:7.69 Mb
ePub File Size:3.81 Mb
ISBN:569-6-29042-443-7
Downloads:87981
Price:Free* [*Free Regsitration Required]
Uploader:Tojalar



The present invention relates to SOC system on a chip , relate in particular to based on SystemVerilog and assert and the collaborative bus verification method and system of task. Verification methodology based on asserting is one of SOC system on a chip SoC functional verification method effectively, and its major advantage is observability and the controllability that has improved SoC design verification.

Assert and can find with comparalive ease the internal error that Sneak Circuits designs, for SoC design verification provides good observability.

Traditional verification method is that input stimulus arrives design to be verified DUV , checks the correctness of signal at output port. Yet the internal error that excitation triggers, likely cannot be delivered to output port. Like this, just cannot check out this mistake. If embed and assert in Validation Code, just can be detected in the wrong place of more approaching generation. Checking based on asserting can language construction ease in use be set up accurate temporal expression.

By checking whether these expression formulas occur, can carry out very simply the inspection of functional coverage, and this coverage rate analysis is for a time series or whole transmission across a plurality of sequential cycle.

The covering analyzing of asserting can directly be used the temporal expression of using in protocol testing or event description, and without additionally writing covering analyzing code, therefore coding can be more flexibly, succinctly. Ahb bus agreement is a part of advanced microcontroller bus architecture AMBA. Wherein, AHB is the system module for high-performance, high clock frequency, and it takes on the maincenter bus of high performance system.

AHB supports processor, on-chip memory, the effective connection between chip external memory and low-power consumption peripheral hardware macroefficiency unit. Compare with other on-chip bus, Wishbone bus structure are simple, and interconnection flexibly, good to the support of customization, also simpler with the interconnection of other on-chip bus, has a wide range of applications equally.

The present invention makes full use of that SystemVerilog asserts and task, can effectively verify bus protocol standard. For the above-mentioned problems in the prior art, the invention provides based on SystemVerilog and assert and the collaborative bus verification method and system of task.

The invention provides based on SystemVerilog and assert and the collaborative bus verification method of task, comprising:. Step 2, carries out attribute according to ahb bus sequential type to ahb bus sequential abstract;. Step 3, asserts description to ahb bus Temporal Order with SystemVerilog according to default condition, or to ahb bus Temporal Order SystemVerilog task description. In one example, in step 2, ahb bus sequential is abstract in inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry, the response of slave piecemeal, water operation, burst transfer or reset.

In one example, in step 3, if ahb bus Temporal Order for inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry or the response of slave piecemeal, assert description with SystemVerilog; If ahb bus Temporal Order is water operation, SystemVerilog task description is used in burst transfer or reset. The invention provides based on SystemVerilog and assert and the collaborative bus verification system of task, comprising:.

Attribute abstract module, abstract for ahb bus sequential being carried out to attribute according to ahb bus sequential type;. Authentication module, for according to default condition, ahb bus Temporal Order being asserted to description with SystemVerilog, or to ahb bus Temporal Order SystemVerilog task description. In one example, ahb bus sequential is abstract in inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry, the response of slave piecemeal, water operation, burst transfer or reset.

In one example, if ahb bus Temporal Order for inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry or the response of slave piecemeal, assert description with SystemVerilog; If ahb bus Temporal Order is water operation, SystemVerilog task description is used in burst transfer or reset.

In one example, also comprise statistical module, for adding up coverage rate. The present invention take full advantage of assert checking advantage, SystemVerilog is asserted to SVA is difficult for the part attribute of definition simultaneously, utilize SystemVerilog task SystemVerilog Task as a supplement, to its description and checking, both collaborative works, respectively get the chief, in the easiest mode, obtain higher coverage rate, reach good verification the verifying results.

Below in conjunction with accompanying drawing, the present invention is described in further detail, wherein:. As shown in Figure 3, verification method of the present invention is: according to ahb bus agreement, list its various timing sequence specification, and by its abstract be various attributes, then utilize SVA and Task to define and describe out these attributes, to realize their monitoring and checking, finally by coverage rate statement, realize coverage rate inspection and analysis.

For the description of attribute bus, because of the advantage of asserting on temporal expression, preferentially select its description. Yet, for the quantitative test across clock period signal value, cannot express by succinct assertion statement, select task statement to describe. Be that this programme is given full play to the advantage of asserting with two kinds of instrument synergies of task.

This Temporal Order is across a plurality of clock period of front and back, and therefore the overlapping if then operation symbol of available SVA is realized. Can realize with the non-overlapping if then operation symbol of SVA. Temporal Order 1 - 6 are all to define description by SVA, and application is asserted and can succinctly must be given expression to its characteristic. And, when attribute is checked, the coverage rate checking mechanism that can utilize SVA to provide, the analysis of simple and effective ground practical function coverage rate.

Yet, if involved in sequential across the data parameters of clock period relatively or there is no the asynchronous sequential of clock, more convenient to its definition with SystemVerilog Task. Following attribute is all described realization by Task.

AHB protocol definition increment and the winding burst transfer of different lengths, in this DUV, what be applied to is 4 bat increment burst transfer, thus only verify this burst temporal characteristics. The foregoing is only the preferred embodiment of the present invention, but protection domain of the present invention is not limited to this.

Any those skilled in the art, in technical scope disclosed by the invention, all can carry out suitable change or variation to it, and this change or change and all should be encompassed in protection scope of the present invention within.

Effective date of registration : Address before : No. The invention discloses a synergy bus validation method and a system based on SystemVerilog assertions and tasks. The validation method comprises a step 1 of listing bus timing of an advanced high performance bus AHB ; a step 2 of conducting attribute abstraction on bus timing of the AHB according to the bus timing type of the AHB; and a step 3 of describing bus timing attributes of the AHB by using the SystemVerilog assertions according to preset conditions, or describing the bus timing attributes of the AHB by using the tasks.

The synergy bus validation method and the system based on SystemVerilog assertions and tasks take full advantages of assertion validation, simultaneously supplement SystemVerilog assertion partial attributes which are not apt to be defined by using the SystemVerilog tasks, describe and verify the partial attributes, obtain high rate of coverage by means of cooperative work of the SystemVerilog assertions and tasks and using advantages of the SystemVerilog assertions and the tasks, and achieve good validation effects.

Based on SystemVerilog, assert and the collaborative bus verification method and system of task Technical field The present invention relates to SOC system on a chip , relate in particular to based on SystemVerilog and assert and the collaborative bus verification method and system of task. Background technology Verification methodology based on asserting is one of SOC system on a chip SoC functional verification method effectively, and its major advantage is observability and the controllability that has improved SoC design verification.

Summary of the invention For the above-mentioned problems in the prior art, the invention provides based on SystemVerilog and assert and the collaborative bus verification method and system of task.

The invention provides based on SystemVerilog and assert and the collaborative bus verification method of task, comprising: Step 1, enumerates ahb bus sequential; Step 2, carries out attribute according to ahb bus sequential type to ahb bus sequential abstract; Step 3, asserts description to ahb bus Temporal Order with SystemVerilog according to default condition, or to ahb bus Temporal Order SystemVerilog task description. In one example, carry out coverage rate statistics The invention provides based on SystemVerilog and assert and the collaborative bus verification system of task, comprising: Sequential is enumerated module, for enumerating ahb bus sequential; Attribute abstract module, abstract for ahb bus sequential being carried out to attribute according to ahb bus sequential type; Authentication module, for according to default condition, ahb bus Temporal Order being asserted to description with SystemVerilog, or to ahb bus Temporal Order SystemVerilog task description.

Accompanying drawing explanation Below in conjunction with accompanying drawing, the present invention is described in further detail, wherein: Fig. Embodiment As shown in Figure 3, verification method of the present invention is: according to ahb bus agreement, list its various timing sequence specification, and by its abstract be various attributes, then utilize SVA and Task to define and describe out these attributes, to realize their monitoring and checking, finally by coverage rate statement, realize coverage rate inspection and analysis.

Step 3, asserts description to ahb bus Temporal Order with SystemVerilog according to default condition, or to ahb bus Temporal Order SystemVerilog task description; In step 3, if ahb bus Temporal Order for inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry or the response of slave piecemeal, assert description with SystemVerilog; If ahb bus Temporal Order is water operation, SystemVerilog task description is used in burst transfer or reset.

Authentication module, for according to default condition, ahb bus Temporal Order being asserted to description with SystemVerilog, or to ahb bus Temporal Order SystemVerilog task description; If ahb bus Temporal Order is for inserting latent period in transmission, idle transmission, busy transmission, slave errored response, the response of slave retry or the response of slave piecemeal, assert description with SystemVerilog; If ahb bus Temporal Order is water operation, SystemVerilog task description is used in burst transfer or reset.

Synergy bus validation method and system based on SystemVerilog assertions and tasks. CNB en. Universal method and platform for verifying compatibility between intellectual property IP core and advanced microcontroller bus architecture AMBA bus interface. CNA en. KRB1 en. TWIB en. Rashinkar et al. USB2 en. Stathopoulos et al. The energy endoscope: Real-time detailed energy accounting for wireless sensor nodes. USB1 en. Hangal et al.

Method for automatically searching for functional defects in a description of a circuit. Performance software instrumentation and analysis for electronic design automation. JPB2 en. JPA en. USA1 en. Method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip. Hartman et al. KRA en. Lahiri et al.

Kim et al. Huang et al.

ERMENI MIMARISI PDF

ISBN 13: 9780971199415

Design reuse of Intellectual Property IP is today a commonly used approach to decrease design and verification time, by using already verified design blocks in multiple chip designs. The IP reuse strategy heavily relies on standardized on-chip interfaces between IP blocks, shifting the verification problem from the block level to the system level. Verification IP VIP has emerged to support not only verification of protocol compliance of design blocks, but also to support system level verification of connected IP blocks from ultimately multiple vendors. As an important part of VIP, assertions describe the temporal actions on block level interfaces. This paper describes how to employ assertions with the state-of-the-art hybrid verification tool Magellan, which combines simulation and formal engines into an effective bug-hunter tool.

KUCH AUR NAZMEIN PDF

Loading...

We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation. Currently, functional verification becomes an intensive challenge phase in the state-of-the-art digital systems development process. Assertion-based verification ABV has emerged as a promising solution to express and verify design properties. SystemVerilog has been accepted by a wide variety of companies and has been supported by most EDA companies in their tools in practice which has totally changed the way designers specify and verify functional requirements and properties of digital systems.

Related Articles